Simulation of an ATM Network Using Verilog
European Design and Test Conference (EURO-DAC'96)
Geneva (Switzerland).
September 16-20, 1996.
ABSTRACT
High level modelling and simulation is a key element in the initial definition
phase of an integrated circuit (ASIC) that is going to form part of a system.
In this paper, the modelling and simulation with Verilog of the
multiplexer/demultiplexer elements of a very high speed ATM (asynchronous
transfer mode) network is presented. The system is built up by several ATM
nodes that insert and extract traffic in a 2.5 Gbit/s channel, and where each
node receives the traffic from an aggregate of on-off sources. Several
simulations were performed with different algorithms for the common medium
access control. Once the access algorithm was determined, several traffic
patterns were also simulated to verify the system performance. The analysis
of results was accomplished by means of a statistical study of the nodes
traffic queue lengths histograms and of the cell delay variations in
communications.
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Related files:
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edac96.pdf |
Paper (Adobe Acrobat Portable Document Format PDF) |
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edac96pp.pdf |
Presentation Slides (PDF) |
Copyright:
© Hütihig GmbH, Heidelberg.
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