On the Way to the 2.5 Gbit/s ATM Network.
ATM Multiplexer/Demultiplexer ASIC
European Design and Test Conference (ED&TC'97)
Paris (France).
March 17-20, 1997.
ABSTRACT
The present paper describes the AMDA integrated circuit
(ATM Multiplexer/Demultiplexor ASIC). The circuit has two operation modes:
in multiplexer mode an ATM low speed flow (up to 622 Mbits/s) is inserted
in the empty slots of a high speed ATM flow (2.5 Gbits/s); in demultiplexer
mode, the cells belonging to the low speed channels are extracted from the
high speed ATM flow. An specific algorithm of distributed control has been
developed, simulated and implemented, in order to guarantee an even bandwidth
distribution independently of the network node position. The circuit is able
to handle 8K connections, with four different qualities of service; it manages
a local queue of up to 16K ATM cells using an external high speed SSRAM.
The maximum clock frequency of the circuit is 155,52 MHz and it has been
processed with the LSI-LOGICÕs LCB500K technology (0,5 mm CMOS).
It contains 34800 equivalent gates, 48 Kbit of single port memory and 8,5 Kbit
dual port memory, using an area of 6,7 x 6,7 mm and it is packaged in a
208 pins QFP.
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edtc97.pdf |
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Presentation Slides (PDF) |
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