Reusing VHDL Soft-Cores by Means of Using Appropriate Worspace
Management and Navigation Tools
Forum on Design Languages (FDL'98)
Lausanne (Switzerland).
September 6-11, 1998.
ABSTRACT
A VHDL Soft-Cores design reuse methodology has to be supported by a new wave
of appropriate tools. Among these design reuse tools, this work presents the
VHDL-ICE Workspace Management and its Navigation tools: The VHDL Design Unit
Navigator, the VHDL Design Hierarchy Navigator, the Simulation Model
Navigator and the VHDL Simulation Debugger.
The advantages offered by the VHDL-ICE environment and, specifically, by the
navigation tools are presented from the tool developers' point of view,
together with the user's perspective provided by a Spanish Telecom company
when developing a circuit reusing Soft-Cores.
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Related files:
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![[Paper (PDF)]](pdficon.gif) |
fdl98.pdf |
Paper (Adobe Acrobat Portable Document Format PDF) |
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fdl98pp.pdf |
Presentation Slides (PDF) |
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