Jacobo Riesco Prieto

TITLE

Telecomunication Engineer by the Escuela Técnica Superior de Ingenieros de Telecomunicación (ETSIT). Universidad Politécnica de Madrid (UPM), Madrid (Spain). 1991.

BOOKS

ASIC Design Methodology. Several authors Ed. by Universidad Politécnica de Madrid. División de Ingeniería Electrónica. Escuela Técnica Superior de Ingenieros Industriales. November 12th, 1996. Madrid (Spain).

PAPERS

A 2.5 Gb/s MUX/DEMUX Implementations for ATM Arquictectures. Christian Reillo, Juan C. Díaz, Jacobo Riesco, Luis Merayo and Pedro Lizcano. IEEE 1995 Global Telecomunications Conference (GLOBECOM 95). November 13-17, 1995 Singapore. ISBN 0-7803-2509-5.
Simulación de una red MTA Utilizando Verilog. Jacobo Riesco, José Luis Conesa, Christian Reillo, Juan C. Díaz and Luis Merayo. X Congress of Systems and Integrated Circuits Design. (DCIS/SICD'95). November 15-17, 1995 Zaragoza (Spain). ISBN 84-600-9269-0. pp. 499-505.
Simulation of an ATM Network Using Verilog. Jacobo Riesco, José Luis Conesa, Christian Reillo, Juan C. Díaz and Luis Merayo. European Desing Automation Conference (EURO-DAC'96). September 16-20, 1996. Geneva (Switzerland). ISBN 3-7785-2545-X. pp. 105-110.
ASIC Multiplexor Demultiplexor ATM. Jacobo Riesco, Juan Carlos Díaz, Carlos Santos, Eduardo Juarez. XI Congress of Systems and Integrated Circuits Design. (DCIS/SICD'96). November 20-22, 1996 Sitges (Spain). ISBN 84-89349-83-5. pp. 213-216.
On the Way to the 2.5 Gbit/s ATM Network. ATM Multiplexer/Demultiplexer ASIC. Jacobo Riesco, Juan Carlos Díaz, Luis A. Merayo, José Luis Conesa, Carlos Santos, Eduardo Juárez. European Design and Test Conference (ED&TC'97). March 17-20, 1997. Paris (France). ISBN 0-8186-7786-4. pp. 218-222. Best industrial ASIC Award at the conference.
Productivity Gains through Re-Use and Quality Improvements of HW Models. A. Allara, A. Balboni, M. Bombana, M. Mastretti, P. Plaza, J. Riesco, J. Schaaf. Second Workshop on Libraries, Component Modeling, and Quality Assurance. April 23-25, 1997. Toledo (Spain). ISBN 84-8102-159-8. pp. 37-45.
Reusing VHDL Soft-Cores by Means of Using Appropriate Worspace Management and Navigation Tools. S. Olcoz, J.L. Avellano, A. Castellví, I. Hidalgo, C. Herrero, P. Plaza, A. Morandeau, J.C. Díaz, J. Riesco. Forum on Design Languages (FDL'98). September 6-11, 1998. Lausanne (Switzerland). ISBN 2-9700180-1-2. pp. 201-207.
Design of an ARM-Based System-On-A-Chip for Pay Phones. J. C. Díaz, J. Riesco, P. Plaza. International Workshop on IP Based Synthesis and System Design (IWLAS'98). December 15-16, 1998. Grenoble (France). pp.101-105. Best IP Prize 1998 at the conference.
The µPP ASIC: Design, Methodologies and Tools for a Pay Phone System-on-a-Chip Based on an ARM Core and Design Reuse. J. Riesco, J. C. Díaz, P. Plaza. IEEE 1999 Custom Integrated Circuits Conference (CICC'99). May 16-19, 1999. San Diego (California, USA). ISBN 0-7803-5443-5. pp. 635-638.
A Neural Network Approach for Generating Solar Irradiation Artificial Series. P. J. Zufiria, A. Vázquez-López, J. Riesco-Prieto, J. Aguilera, L. Hontoria. International Work-Conference on Artificial and Natural Neural Networks (IWANN'99). June 2-4, 1999. Alicante (Spain). In Engineering Applications of Bio-Inspired Artificial Neural Networks. Ed. Springer-Verlag, Berlin Heidelberg, 1.999, ISBN: 3-540-66068-2. pp. 874-883.
Improved Generation of Hourly Solar Irradiation Artificial Series Using Neural Networks. L. Hontoria, J. Riesco, P. Zufiria, J. Aguilera. International Conference on Engineering Applications of Neural Networks (EANN'99). September 13-15, 1999. Warsaw (Poland). In Engineering Applications of Neural Networks. Ed. Wlodzislaw Duch, 1999. ISBN 83-7174-512-5. pp. 87-92.
The TEMA Advanced Pay Phone System Digital Board. J. Riesco, J. C. Díaz, P. Matas, P. Y. Plaza. XIV Design of Circuits and Integrated Systems Conference. (DICS'99). November 16-19, 1999. Palma de Mallorca (Spain).

IMPARTED COURSES AND SEMINARS

Simulación Funcional en Verilog. (Functional Simulation with Verilog). Telefónica Investigación y Desarrollo, Sept. 23th-26th, 1996 (25 h). Madrid (Spain).

ATTENDED COURSES AND SEMINARS

VLSI Signal Processing. Departamento de Ingeniería Electrónica (DIE-UPM). Universidad Politécnica de Madrid, June 20-21, 1990 (10 h). Madrid (Spain).
Design For Testability Using Panther Expert. Philips ED&T, May 19-20, 1992. Eindhoven (The Netherlands).
Getting the Most from Cell Ensemble. Advanced Thecnical Workshop. Cadence regional offices, October 12, 1994. Paris (France).
Designing with FLEX 10K and Synopsys Synergy. By Altera. Telefónica I+D, June 12, 1996. Madrid (Spain).
VHDL as System Design Language. Tecnología y gestión de la Innovación (TGI), October 23-24, 1996. Madrid (Spain).
Introducción a ATM (Introduction to ATM). Telefónica I+D, November 7, 14, 18-20, 1996 (25 h). Madrid (Spain).
Advanced Timing Analysis Tools for Digital Systems. By Quad Design. Telefónica I+D, February 13-14, 1997. Madrid (Spain).
Análisis y Diseño Orientado a Objetos (Object Oriented Analysis and Design). By Aldebarán Sistemas. Telefónica I+D, December 1-5, 1997 (35 h). Madrid (Spain).
Gestión de Proyectos (Project Management). By Hans-Hofmann Reinecke Industrial Consulting. Telefónica I+D, April 14-15, 1998 (20 h). Madrid (Spain).
Managing and Reusing VHDL Soft-Cores. REQUEST Technical Workshop. SIDSA, October 22nd, 1998. Tres Cantos, Madrid. (Spain).
Redes LAN-WAN. Tecnología y Sistemas (LAN-WAN Networks. Technology and Systems). Telefónica I+D, April 6-9, 1999 (25 h). Madrid (Spain).

POSTGRADUATE COURSES

PhD Courses in Circuitos y Sistemas Electrónicos Integrados. (Integrated Electronic Systems and Circuits). Universidad Politécnica de Madrid. ETSI Telecomunicación.
- Course 1997/1998.
  - Arquitecturas Digitales Soportadas en VLSI. (VLSI Digital Architectures. 6 credits).
  - Codiseño Hardware/Software. (Hardware/Software Codesign. 6 credits).
  - Síntesis de Alto Nivel para Diseño Electrónico. (High Level Synthesis for Electronic Design. 6 credits).
- Course 1998/1999.
  - Diseño de Sistemas Basados en Tarjetas Inteligentes. (Smart Card Systems Design. 6 credits).
  - Procesamiento de Imágenes y Señales Biomédicas.. (Biolmedical Images and Signals Processing. 6 credits).

COPYRIGHTS AND PATENTS

ADAM: Algoritmo Distribuido de Acceso a un Medio compartido. (ADAM: Algorithm for Distributed Access to a shared Medium). Jacobo Riesco, Luis Antonio Merayo, Alenjandro Alonso, José Luis Conesa. Copyright pending.

Circuito integrado para la extracción y adición de tráfico en modo de transferencia asíncrono. (Integrated Circuit for traffic extraction and addition in asynchronous transfer mode). Jacobo Riesco, Juan Carlos Díaz, José Luis Conesa, Luis Antonio Merayo. Patent request number 9802714. Oficina Española de Patentes y Marcas.

AWARDS

The award for the Best Industrial ASIC at ED&TC'97.
Best IP Prize 1998 at IWLAS'98.

OTHER INVESTIGATION WORKS

Optimización Global: Aplicación en el Entrenamiento de Redes Neuronales. (Global Optimization. Application to Neural Networks Trainning). ETSIT-UPM. December 1993.

WORK EXPERIENCE

Telefónica Investigación y Desarrollo. Hardware Technology Division. Emilio Vargas, 6. 28043 Madrid (Spain).
Since 1992 till now.

I have worked in the following projects:
- Hardware (ASIC, FPGA and PCB designs):
  - DEPTH. ASIC for 2 Mbit/s HDLC data transmission on PCM channels. GAME-I ESPRIT-2 Project 5083 (number 052). September 1992 - June 1993.
  - PIC. Development of a Peripherial Interrupt Controller ASIC for the 680x0 microprocessors family. July 1993 - September 1993.
  - ICM2/CMC. 2.5 Gbit/s ATM switch chipset. Developed in cooperation with ST (SGS-Thomsom) Milan (Italy). STRATOSPHERIC RACE-2 Project 14432. February 1994.
  - TRJM. ATM-SDH Mapper ASIC. Handles STM-0, STM-1 and STM-4 (i.e. up to 622 Mbit/s) SDH formats. May 1994 - October 1994.
  - AMDA. ATM Mux/Demux ASIC (622Mbit/s to 2.5 Gbit/s). Best ASIC Award at ED&TC'97. GAME-II ESPRIT-3 Project 7501 (number B066). January 1995 - June 1997.
  - TB_AMDA. AMDA Test PCB. May 1997 - August 1997.
  - PRI-II. ASIC for PCM Switching. August 1997 - December 1997.
  - µPP. Design of an ASIC with an embedded ARM microprocessor for public telephony applications. Best IP Prize at IWLAS'98. TOMI ESPRIT-4 Project 20724. January 1998-February 1999.
- Software:
  - EVEREST. ESPRIT-2 Project 2318. Development of CAD Tools for ASIC Test automation (Automatic Test Pattern Generation, Full scan insertion, etc.). The tools were developed in an Unix environment using the C language and with an X-Windows graphics user interface (GUI). September 1991 - December 1992.
  - REQUEST. ESPRIT-4 Project 20616. Reuse and Quality Estimation Tools for ASICs' design. October 1996 - October 1998.
- Other projects:
  - PRENDA. Definition of ASIC Design Methodologies. GAME-II ESPRIT-3 Project 7501 (Number B029). January 1994 - November 1995.
  - SAM. Automatic GSM telephony coverage measurements system. September 1997.
  - Participation in the elaboarion of the EDAA System Design Technology Roadmap for the next five years (1998-2002)
I have a deep knowledge of the following tools and environments (which I use or have used in my daily work):
- CAD tools for VLSI asic and board design:
  - The Verilog Hardware Description Language and the Verilog-XL logic simulator.
  - The VHDL Hardware Description Language and the QuickSim logic simulator.
  - The Synopsys Logic Synthesis products (Design Compiler, Design Time, HDL Compiler).
  - The Motive static timing analyzer.
  - The Cadence Custom IC Design software (Cell Ensemble, Composer, Virtuoso).
  - The Cadence Board Level Design software (Concept).
- Software development tools:
  - The C programming language.
  - CVS Concurrent Version System.
  - DDTS Distributed Defect Tracking System.
  - Purify Memory leaks and runtime access errors detector.
  - XDesigner GUI development tool.
  - lex and yacc, awk, etc. Parsing and lexical analizer generation tools for compilers' development.
  - Visual Basic.
- Offimatic tools:
  - Word Proccessors: FrameMaker, Word, Word Perfect .
  - Data bases: Access, dBase-III+.
  - Spreadsheets: Excel.
  - Presentations: Power-Point.
  - Project management: Microsoft Project.
- Operating systems:
  - Unix (SunOS, Solaris, Interactive & Linux).
  - DOS.
  - Windows 3.1 & 3.11 (WFG).
  - Windows 95.

LANGUAGES

Spanish. (Birdth language).
Galician Language. (Birdth language).
English.

Address: C/ Emilio Vargas, 6; 28043 Madrid (Spain)
Phone: (+34) 91 337 48 54
URL: http://www.geocities.com/Paris/6221
E-Mail: jacobo@geocities.com; jacobo@tid.es
Birdthdate: August 1st 1966. Vigo (Pontevedra) - Spain.


Curriculum en Español	Currículo en Galego

Jacobo Riesco's main page